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? semiconductor components industries, llc, 2002 january, 2002 rev. 6 1 publication order number: cs51220/d cs51220 feed forward voltage mode pwm controller with programmable synchronization cs51220 is a single output pwm controller with switching frequency up to 500 khz. the feed forward voltage mode control provides excellent line regulation for wide input range. this pwm controller has a synchronization output allowing programmable phase delay. for overcurrent protection, the asoft hiccupo technique effectively limits the output current with maximum flexibility. in addition, this device includes such features as: soft start, pulsebypulse current limit, programmable foldback current limit, voltsecond clamping, maximum duty cycle, overvoltage and undervoltage protection, and synchronization input. the cs51220 is available in 16 so narrow surface mount package. features ? constant frequency feed forward voltage mode control ? programmable pulse by pulse overcurrent limit ? programmable foldback overcurrent limit with delay ? soft hiccup overcurrent protection with programmable foldback ? frequency synchronization output with programmable phase delay ? synchronization input to higher or lower frequency ? direct connection to external opto isolators ? logic gate output signal ? accurate voltsecond clamping ? programmable soft start ? logic input to disable ic ? line overvoltage and undervoltage monitoring ? 3.3 v 3% reference voltage output http://onsemi.com device package shipping ordering information so16 48 units/rail so16 2500 tape & reel so16 d suffix case 751b a = assembly location wl, l = wafer lot yy, y = year ww, w = work week c t uv 1 cs51220 awlyww 16 synci ov disable i sense ff i set comp v ref ss v cc v sd gnd synco v o pin connections and marking diagram 1 16 cs51220ed16 cs51220edr16
cs51220 http://onsemi.com 2 figure 1. application diagram, 48 v to 3.3 v converter v cc i sense v o gnd ss synci synco disable comp ov uv i set v sd c t v ref ff cs51220 enable sync out c8 390 pf c7 1000 pf r8 64.9 k r6 7.5 k r5 10 k r7 150 k r9 510 k r11 510 k r10 15 k r12 11.8 k c6 0.1 m f c9 1000 pf r14 2.0 k sync in c10 0.1 m f c11 1.0 m f v dd out out gnd gnd nc ina v dd ncp4414 u4 u1 q1 mtb20n20e c13 100 pf r16 10 200 v c12 680 pf r23 10 d5a mbrb2535ctl c17 330 m f 20:5 c18 330 m f v out v o rtn 3.3 v @ 5.0 a r21 40.2 k r22 24.3 k c15 0.022 m f r20 2.21 k c14 100 pf u3 tlv431asnt1 r19 3.92 k r18 1.0 k r17 182 u2 moc213 t2 t1 70:1 r15 10 k mmsd4148t1 d4 36 r14 r13 100 c12 100 pf v in gnd c1 0.2 m f 1.0 m h l2 100 v c2 0.1 m f 500 v r2 174 k c4 470 pf c3 1.5 m f 100 v r1 100 k d1 9.1 v mmsz5239b q2 mmft1n10e d2 15 v mmsz5245b c5 0.1 m f r3 10 d3 mmsd4148t1 r4 10 l1 6.8 m h d5b mbrb2535ctl 3672 v r23 220 r24 3.3 k
cs51220 http://onsemi.com 3 maximum ratings* rating value unit operating junction temperature, t j 150 c storage temperature range, t s 65 to +150 c esd susceptibility (human body model) 2.0 kv thermal resistance, junctiontocase, r q jc 28 c/w thermal resistance, junctiontoambient, r q ja 115 c/w lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. maximum ratings pin name pin symbol v max v min i source i sink gate logic output v o 20 v 0.3 v 100 ma 100 ma current sense input i sense 6.0 v 0.3 v 10 ma 10 ma timing capacitor c t 6.0 v 0.3 v 10 ma 10 ma feed forward ff 6.0 v 0.3 v 10 ma 100 ma error amp output comp 6.0 v 0.3 v 10 ma 10 ma feedback voltage v fb 6.0 v 0.3 v 10 ma 10 ma sync input synci 20 v 0.3 v 10 ma 10 ma power down input disable 20 v 0.3 v 10 ma 10 ma undervoltage uv 6.0 v 0.3 v 10 ma 10 ma overvoltage ov 6.0 v 0.3 v 10 ma 10 ma current set i set 6.0 v 0.3 v 10 ma 10 ma soft start ss 6.0 v 0.3 v 10 ma 10 ma power supply v cc 20 v 0.3 v 10 ma 50 ma sync output synco 20 v 0.3 v 100 ma 100 ma reference voltage v ref 6.0 v 0.3 v internally limited 10 ma sync delay v sd 6.0 v 0.3 v 1.0 ma 1.0 ma ground gnd n/a n/a 50 ma n/a
cs51220 http://onsemi.com 4 electrical characteristics (40 c < t a < 85 c; 40 c < t j < 125 c; 4.7 v < v cc < 16 v; c t = 390 pf; unless otherwise specified.) characteristic test conditions min typ max unit supply voltage/current start threshold 4.0 4.4 4.7 v stop threshold 3.3 3.8 4.1 v hysteresis start stop 400 600 1000 mv i cc @ startup v cc < uvl start threshold 500 m a i cc operating, low v cc 4.7 v < v cc < 10 v 7.5 ma i cc operating, high v cc 10 v < vcc < 16 v 9.0 ma reference voltage total accuracy 0 ma < i ref < 2.0 ma 3.2 3.3 3.4 v line regulation i ref = 2.0 ma 6.0 20 mv load regulation 0 ma < i ref < 2.0 ma, v cc = 8.0 v 6.0 15 mv operating life shift t = 1000 hrs., note 2 4.0 20 mv fault voltage 2.8 2.95 3.1 v v ref ok voltage 2.9 3.05 3.2 v v ref ok hysteresis 50 100 150 mv current limit v ref = 2.5 v 2.0 25 65 ma oscillator frequency accuracy 223 266 309 khz temperature stability note 2 8.0 % max frequency note 2 500 khz duty cycle 80 85 90 % peak voltage note 2 1.9 2.0 2.1 v valley voltage note 2 0.85 0.90 0.98 v discharge current v ct = 1.5 v 0.70 0.85 1.05 ma charge current v ct = 1.5 v 127 150 183 m a synchronization synci input threshold f sync = 500 khz 1.0 2.0 3.0 v synci input resistance v sync = 0.5 50 150 250 k w minimum sync frequency reduction of nominal frequency. 25 % minimum input sync pulse width 200 ns synco output high r synco = 5.0 k, v cc = 8.0 v 5.0 6.5 7.5 v synco output low sink 1.0 ma, v sd = 2.5 v 0.2 0.4 v synco delay time v ct = 1.5 v, toggle v sd 100 200 300 ns 2. guaranteed by design. not tested in production.
cs51220 http://onsemi.com 5 electrical characteristics (continued) (40 c < t a < 85 c; 40 c < t j < 125 c; 4.7 v < v cc < 16 v; c t = 390 pf; unless otherwise specified.) characteristic unit max typ min test conditions output (continued) high saturation voltage v cc v o , v cc = 10 v, i source = 100 m a 1.4 2.0 v low saturation voltage v o gnd, i sink = 100 m a 0.7 1.0 v pull down resistance i sink = 100 m a 25 50 75 k w rise time v cc = 10 v, 1.0 v < v o < 6.0 v; 50 pf load 35 80 ns fall time v cc = 10 v, 1.0 v < v o < 6.0 v; 50 pf load 25 50 ns feed forward discharge voltage i ff = 2.0 ma 0.25 0.35 0.45 v discharge current ff = 1.0 v 2.0 10 30 ma ff to v o delay connect v o to ff, measure min. pulse width. 50 75 150 ns ff clamp voltage 1.15 1.3 1.45 v comp switch off voltage v ff = 0.2 v, ramp down v comp v ff = 0.2 v, ramp down v comp 40 c 0.8 1.4 1.4 1.6 1.7 1.7 v v overcurrent protection overcurrent comparator dc offset 180 200 215 mv i sense attenuation d v iset / d v isense 0.9 0.94 0.98 v/v i sense input resistance d v isense = 0 v 40 82 150 k w i sense to gate delay v iset = 0.5 v 50 100 175 ns i set foldback sink current i set = 0.5 v, ss = 1.5 v and i sense = 0.5 v 12 15 18 m a external voltage monitors overvoltage threshold ov pin increasing 1.9 2.0 2.1 v ov hysteresis current ov = 2.15 v 10 12.5 15 m a undervoltage threshold uv pin decreasing 0.95 1.00 1.05 v uv hysteresis 25 75 125 mv soft start charge current ss = 1.5 v 35 50 65 m a discharge current ss = 1.5 v, uv = 1.5 v 4.0 5.0 7.0 m a oc delay discharge current ss = 2.85 v, i set = 0.5, i sense = 0.5 v 35 50 65 m a ss clamp voltage 2.7 2.9 3.1 v discharge voltage 0.25 0.3 0.35 v soft start fault voltage ov = 2.5 v or uv = 0.85 v 0.1 0.2 v hiccup delay discharge voltage 0.08 0.1 0.12 v disable disable input threshold 1.0 2.0 3.0 v disable input resistance v disable = 0.5 v 50 150 250 k w disable operation current, low v cc 4.7 v < v cc < 10 v 800 m a disable operation current, high v cc 10 v < v cc < 16 v 1600 m a
cs51220 http://onsemi.com 6 package pin description package pin # 16 lead so narrow pin symbol function 1 v o logic output connecting to external gate driver. 2 gnd ground. 3 v cc supply voltage. 4 v ref 3.3 v reference voltage output. 5 i set voltage at this pin sets pulsebypulse overcurrent thresh- old. when the i sense exceeds i set for a sustained period of time, a sink current is generated at this pin. along with exter- nal resistors, this current provides a foldback overcurrent threshold. the sink current is disabled periodically for restart. 6 i sense current sense input for overcurrent protection. 7 ov overvoltage protection monitor. 8 uv undervoltage protection monitor. 9 c t timing capacitor c t determines oscillator frequency. 10 synci by applying sync pulses to this pin, the ic can be synchro- nized to frequencies ranging from 25% slower to several times faster than the internal oscillator frequency. 11 disable disable mode input pin. a voltage greater than 3.0 v turns off the whole ic. 12 ff feed forward input for pwm ramp. this pin allows external connection to make the ramp adjustable to the input line. 13 comp this pin carries feedback error signal from an external ampli- fier. internally, it connects to the pwm controller. 14 ss a capacitor is connected to this pin for soft start and soft hiccup timing. 15 v sd the voltage at this pin programs the delay of the synco output in reference to the internal oscillator. 16 synco sync output.
cs51220 http://onsemi.com 7 - + - + + - - + - + - + - + v cc disable uvl comparator v ref = 3.3 v v ref comp soft hiccup i sense i set comp 200 mv + gnd ff synco v sd synci c t osc s r q uv comp 1.0 v 2.0 v v o uv ov ss 0.3 v v ref charge off 3.1 v ss clamp fault latch s rq q ss comp set dominant ov comp clk oc ifoldback i lim ss 1.3 v min pwm comp x0.94 + ss low figure 2. block diagram discharge reset dominant ss low ss ss discharge ss
cs51220 http://onsemi.com 8 applications information theory of operation feed forward voltage mode control conventional voltage mode control uses a fixed ramp signal for pulse width modulation, typically utilizing the oscillator output as the ramp signal. since the only feedback signal comes from the output, this results in inferior line regulation and audio susceptibility. a significant improvement in line regulation and line transient response can be achieved using feed forward voltage mode control, implemented using the cs51220 controller. the enhancement comes from generating the ramp signal using a pullup resistor from the ff pin to the line voltage and a capacitor to ground. the slope of the ramp then depends on the line voltage. at the start of each switch cycle, the capacitor connected to the ff pin is charged through the resistor connected to the input voltage. meanwhile, the v o pin goes high to turn on a power mosfet through an external gate driver. when the rising ff pin exceeds the comp input pin, as driven through the regulation feedback loop, v o goes low and turns off the external switch. simultaneously, the ff capacitor is quickly discharged and set for the next switching cycle. overall, both input and output voltages control the dynamics of the duty cycle. as illustrated in figure 3, with a fixed input voltage the output voltage is regulated solely by the error amplifier. for example, an elevated output voltage pulls down the comp pin through an external error amplifier. this in turn causes duty cycle to decrease. on the another hand, if the input voltage varies, the slope of the ff pin ramp reacts correspondingly and immediately. as an example shown in figure 4, when the input voltage goes up, the slope of the ramp signal increases, which reduces duty cycle and counteracts the change. for line variations, feed forward control requires less response from the error amplifier, which improves the transient speed and dc regulation. figure 3. pulse width modulated by the output voltage with a constant input voltage v in comp ff v out c t v o figure 4. pulse width modulated by the input voltage with a constant output voltage v in comp ff v out c t v o the feed forward feature can also be employed for voltsecond clamp, which limits the maximum product of input voltage and switch on time. this clamp is used in circuits, such as forward and flyback converters, to prevent the transformer from saturating. calculations used in the design of the voltsecond clamp are presented in the design guidelines section on page 12.
cs51220 http://onsemi.com 9 v cc power up and fault conditions during power up, an undervoltage lockout comparator monitors v cc and disables v ref , (which in turn disables the entire ic), until the v cc voltage reaches its start threshold. hysteresis prevents achatteringo caused by the source impedance of the v cc supply. v ref can also be disabled using the disable input pin, which is active high. an internal pulldown resistor ensures the ic will start up if the disable pin is allowed to float. in v cc or disable lockout mode, the output stage is held low by the output pulldown resistance. after v ref turns on, there are three conditions that can cause fault mode: 1. the 3.3 v v ref is below regulation, 2. the ov pin rises above overvoltage threshold, or 3. the uv pin falls below undervoltage threshold. fault detection will cause the v o output to go low and the ss pin to discharge. the uv and ov inputs are typically used to monitor the input line voltage. the undervoltage comparator has a builtin hysteresis voltage, while the hysteresis for the ov comparator is programmable through a current sourced from the pin when above the threshold, and the equivalent external resistance. the fault condition can only be reset after the ss pin has been completely discharged and all faults have been removed. after a fault is removed or upon initial startup, the ss pin charges at a rate determined by an internal charge current and an external capacitor. the rising voltage on the ss pin will override the regulation feedback voltage on the comp pin and clamp the duty cycle, helping to reduce any inrush current during startup. the duration of the soft start is typically set with a capacitor from 0.01 m f to 0.1 m f. overcurrent protection the cs51220 uses the asoft hiccupo technique to provide an adjustable and predictable overcurrent limit. by choosing external component values the designer can select pulsebypulse current limit, soft hiccup current limit or hard hiccup limit. normal pulsebypulse current limit can be obtained by selecting the i set resistor values for a low thevenin resistance to the i set pin. however with normal pulsebypulse current limit, the secondary currents during short circuits may be several times the maximum output current. soft hiccup limit can be obtained by setting the i set resistor values for a higher thevenin resistance. during overcurrent conditions, the i set level will fold back, after a short delay, to reduce the pulse by pulse threshold. if desired, the short circuit current can be chosen to be equal to or even less than the maximum output current. during soft hiccup the circuit will periodically disable the foldback and attempt to restart. hard hiccup limit can be obtained by setting the i set resistor values so that the i set pin is held below 200 mv during foldback. during overcurrent conditions, the i set level will fold back, after a short delay, preventing any gate pulses. w hen the ss capacitor is completely discharged, the circuit will attempt restart. this configuration provides the lowest power dissipation during short outputs. the circuit functions can be best described by discussing the block diagram and illustrations of expected waveforms. actual waveforms, values and circuit configurations from a design will be used. the design is from the 5.0 v supply of a dual synchronized converter. the current is monitored with a voltage at the i sense pin. the i sense signal is slightly attenuated dc shifted by 200 mv, and is compared with the threshold voltage programmed by the voltage at the i set pin. if the current signal reaches the threshold voltage, the overcurrent comparator resets the v o latch and terminates the v o pulse. the overcurrent comparator has a maximum common mode input voltage of 1.8 v. however, an i set voltage below 1.0 v is desirable for reducing the comparator's propagation delay. during initial turnon of the power supply, normal pulsebypulse overcurrent control is used to protect the power supply switches. this is accomplished by comparing the voltage at the i sense input to the voltage at the i set pin and using this to limit the duty factor of v o , the gate drive signal. this current limit control is maintained until the ss voltage reaches 2.9 v.
cs51220 http://onsemi.com 10 the block diagram of the soft hiccup circuit is shown in figure 5. when overcurrent occurs and the ss is above 2.9 v, the oc pulses set the oc latch. the output of the oc latch turns on the oc delay discharge current to ramp down the ss voltage. this ss discharge ramp down is at a rate of 50 m a while the ss voltage is above 2.8 v. the level between 2.9 v and 2.8 v is called the hiccup delay discharge voltage. the time to cross this voltage creates a short delay. this delay is useful so that a quick transient overcurrent condition can be controlled and still allow the supply to return immediately to normal operation. after r eaching the hiccup delay discharge voltage, the ss current is reduced to 5.0 m a and the i set foldback current is turned on at 15 m a. it is the i set foldback current that adjusts the i set level to establish a new lower i sense current limit level. see figure 6 for details. figure 5. the block diagram of the soft hiccup operation ss low clk oc ss + + one shot n00c reset peak comp 2.9 v trig oc latch delay comp 2.8 v ss discharge on s r foldback q a circuit monitors the oc pulses. if the oc pulses cease for 50 m s, the notovercurrent (nooc) signal is generated. this nooc signal resets the oc latch and allows the ss capacitor to charge back up allowing the output to reestablish regulation. for an equivalent circuit shown in figure 6, the i set current reduces the overcurrent threshold and sets the new threshold at v i(set) (3.3 i set r1) r2 (r1 r2) v ref i set pin r1 r2 i set figure 6. the voltage divider used at the i set pin allows the i set foldback current to reduce the overcurrent threshold the nooc or ss low (v ss < 0.3 v) signal can reset oc latch at any time. this event turns off i set foldback and allows the recharging of the ss capacitor. therefore, the ic allows the power supply to restart periodically or after the overcurrent condition is cleared. the oc latch can not be set until the ss capacitor is fully charged. to implement ahard hiccupo which disables the v o completely when the ss voltage is ramping down, select a resistor value greater than 3.3 v/i set for r1 in figure 6, and saturate the internal i set current source. since the saturation voltage is less than the dc shift applied to the i sense signal, the oc comparator output is always high and in turn keeps the v o low. figure 7 demonstrates the interactions among the voltage of ss, i set and internal signal oc. figure 8 further describes the specifications associated with the soft hiccup. the ratio among the charge time, delay time and discharge time is given at the bottom of figure 8. ss i set oc 50 m s 2.9 v 2.8 v 0.3 v figure 7. illustrative waveforms of the soft hiccup operation charge voltage charge current figure 8. the ss pin voltage under ramp up and overcurrent condition and associated specifications. 26 discharge voltage oc delay dischage current dischage current 1 250 hiccup delay discharge voltage
cs51220 http://onsemi.com 11 the effect of the soft hiccup can be observed in figure 9, which shows the output voltage as load increases. the output is maintained at the regulation value of 5.0 v until it goes into current limit. at the point of overcurrent inception (a), the current limit level changes to a lower level (b). the switchback to a lower current limit level can be seen as the bottom curve in figure 9. 0 load current (a) figure 9. overcurrent in a 5.0 v output converter using soft hiccup output voltage (v) 46 6 2 0 2 5 4 3 1 a b a typical overload scenario is shown in figure 10. the top trace is the voltage on the soft start (ss) pin. the initial high discharge rate can be seen transitioning to a 40 ms discharge period. during this period the i set establishes a lower current limit level. the bottom trace shows the output current. the initial current spike is the output capacitors discharging. the next level around 4.0 a is the short circuit current level set by the i set current. the output then turns off allowing the current to reduce to a level that does not cause overcurrent pulses. this releases the ss pin to ramp back up. during ramp up, the output is still shorted as noted by the 8.0 a current level. when ss reaches the 2.9 v level, the short is again recognized and i set is turned back on shifting the short circuit current level. figure 10. overload current and soft start waveforms the middle trace is a digitizing `scope trace of the current sense line. the scope interprets the voltages as an average voltage. this voltage is actually a narrow duty cycle peak voltage representing the peak current level in the switching transistor. the actual peak voltages can be seen in the figure 11. the peaks are 0.85 v at full load, reducing to 0.6 v peak at the reduced short circuit level. the 1.1 v peak is the full short circuit current while ss ramps back up. the 0.32 v level is the normal load resistance, while i set is still on. the 1.0 v surge is created by ramp up into a normal 5.0 a load and followed by the 0.85 v at normal load. figure 11. overload current and i sense voltage peak detect setting oscillator and synchronization the switching frequency is programmable through a capacitor connected to the c t pin. when the c t pin voltage reaches peak voltage (2.0 v), the internal discharge current discharges the c t capacitor and v o stays low. when the c t voltage declines to valley voltage (0.9 v), the current source toggles to charge current and ramps up the c t pin. this starts a new switching cycle. the duty cycle of the oscillator determines the maximum pwm duty cycle. the switching frequency of the ic can be synchronized to an external frequency presented to the synci pin. when pulses with amplitude over synci input threshold are detected, the c t pin immediately ramps down the external capacitor and the v o pin is forced low. a new switching cycle begins when the c t pin reaches valley voltage. during synchronization, the oscillator charge current is reduced by 80 m a, while discharge current is increased by 80 m a. this effectively slows down the internal oscillator to avoid any race condition with the sync frequency. as a result, the sync frequency can be either higher or lower than the internal oscillator frequency. cs51220 is able to synchronize up to 500 khz and down to 25% below c t frequency. the maximum duty cycle clamp is raised to 92% in synchronization mode. the original oscillator frequency is restored upon the removal of sync pulses.
cs51220 http://onsemi.com 12 figure 12. synchronization input timing figure 12 shows the sync input from one cs51220 into another. the delay between receiving the sync input and the start of the next switching cycle is 423 ns. this delay must be taken into account when establishing the total delay between two regulators. the synco pin provides outgoing synchronization pulses whose delay can be programmed by setting the voltage on the v sd pin. the feature allows two converters to run at interleaved phases. this implementation significantly reduces the input ripple, and thus the number of input capacitors. the phase delay is achieved by turning on synco output only after the c t pin voltage reaches the v sd voltage. therefore, the phase delay varies linearly with the v sd voltage. the synco output is reset during the falling edge of the c t pin. for minimum phase delay (~ 240 ns), tie the v sd pin to the ground. to entirely disable the synco output, connect the v sd pin to v ref . the waveform in figure 13 shows the c t ramp crossing the v sd voltage set at 1.41 v. figure 13. synchronization output timing the delay from the point of crossing to the output of the sync signal is 240 ns. the time for the sync out voltage is measured at the +2.0 v level, which is the level that triggers the next cs51220. the desired effect on the input ripple is illustrated in figure 14. this is the input current for two power converters operating from a 36 v line. figure 14. input current ripple with different overlap conditions the top waveform in figure 14 is the input current with the two supplies operating out of phase. the next down shows the same supplies but with both conduction times occurring simultaneously. the greatly increased ripple current can be observed. the last two waveforms are the two converters shown individually when operating out of phase. design guidelines program voltsecond clamp feed forward voltage mode control provides the voltsecond clamp which clamps the product of the line voltage and switch on time. for the circuit shown in figure 15, the charging current of the c ff can be considered as a constant current equal to v in /r ff , provided v in is much greater than the ff pin voltage. then the voltsecond clamp provided by cs51220 is given by v in t on(max) 1.0r ff c ff v in rff cff ff pin figure 15. an rc network provides both voltsecond clamp and feed forward control select the time constant of the ff pin rc network to provide desirable voltsecond clamp.
cs51220 http://onsemi.com 13 program oscillator frequency cs51220 requires an external capacitor to program the oscillator frequency. the internally trimmed charge/discharge current determines the maximum duty cycle. the capacitor for a required switching frequency f s can be calculated by: ct 13400 f s 95 where: c t = timing capacitance is in pf f s = switching frequency is in khz figure 16 shows the relationship of c t and f s . 200 c t (pf) figure 16. operating frequency frequency (khz) 600 550 500 450 400 350 300 250 200 150 100 100 300 400 500 600 synchronized dual converters with soft hiccup and feed forward the circuits shown in figures 17 and 18 illustrate typical applications for a dual output supply using independent but synchronized converters. these circuits demonstrate the use of the soft hiccup, feed forward, voltsecond control and synchronization features of the cs51220. in figure 17, the feed forward circuit has a voltsecond constant of 82 v/ m s. this would limit the duty factor to 0.51 at 48 v input. with a turns ratio of 4:1 on the power transformer and 48 v input, a duty factor of 0.46 is required for 5.0 v output. this converter serves as the master synchronization generator. the voltage on the v sd pin establishes the delay as it is compared to the ramp generated on the c t pin. adjustable synchronization allows the conduction time for the two converters to be adjusted so that they are not on at the same time. this greatly reduces the ripple current from the 48 v source. in figure 18, the feed forward circuit has a voltsecond constant of 63 v/ m s. this would limit the duty factor to 0.39 at 48 v input. with a turns ratio of 4:1 on the power transformer and 48 v input, a duty factor of 0.33 is required for 3.3v output.
cs51220 http://onsemi.com 14 figure 17. additional application diagram, 5.0 v output converter used as sync master for the dual converter v cc i sense v o gnd ss synci synco disable comp ov uv i set v sd c t v ref ff cs51220 enable1 c4 390 pf c38 1000 pf r5 64.9 k r3 7.5 k r2 10 k r4 150 k r7 511 k r21 511 k r8 15 k c3 0.1 m f c35 1000 pf r14 2.0 k sync in c7 0.1 m f c18 1000 pf v dd out out gnd gnd nc ina v dd ncp4414 u4 u1 q2 irf634s c10 100 pf r13 10 200 v c12 680 pf r15 10 d5a mbrb2535ctl c11 330 m f 20:5 c9 330 m f v out v o rtn 5.0 v @ 5.0 a r19 40.2 k c36 1000 pf r20 13.3 k c14 0.022 m f r18 10 k c13 100 pf u3 tlv431asnt1 r48 3.92 k r17 1.0 k r16 182 u2 moc213 t2 t1 70:1 r10 10 k mmsd4148t1 d1 36 r12 r11 100 c6 100 pf v in c16 0.2 m f 1.0 m h l2 100 v c37 0.1 m f 500 v r6 174 k c5 470 pf c1 1.5 m f 100 v r1 100 k d4 9.1 v mmsz5239bt1 q1 mmft1n10e d3 15 v mmsz5245bt1 c2 0.1 m f r22 10 d2 mmsd4148t1 r23 10 l1 6.8 m h d5b mbrb2535ctl gnd 3672 v bst1 tp1 v in tp2 tp3 tp4 sync r9 11.8 k 1.25 v
cs51220 http://onsemi.com 15 figure 18. additional application diagram, 3.3 v output converter synchronized to the 5.0 v converter v cc i sense v o gnd ss synci synco disable comp ov uv i set v sd c t v ref ff cs51220 enable2 sync out c20 390 pf c39 1000 pf r28 64.9 k r26 5.11 k r25 10 k r27 150 k r29 511 k r31 511 k r30 15 k c19 0.1 m f c33 1000 pf r33 2.0 k sync c21 0.1 m f c24 1.0 m f v dd out out gnd gnd nc ina v dd ncp4414 u4 u5 q3 mtb20n20e c28 100 pf r40 10 200 v c25 680 pf r39 10 d8a mbrb2535ctl c26 330 m f 20:5 c27 330 m f v out v o rtn 3.3 v @ 5.0 a r44 40.2 k r45 24.3 k c29 0.022 m f r43 2.21 k c30 100 pf u7 tlv431asnt1 r47 2.21 k r42 1.0 k r41 182 u6 moc213 t4 t3 70:1 r36 10 k mmsd4148t1 d7 36 r35 r34 100 c23 100 pf v in r24 137 k c31 470 pf c32 1.5 m f 100 v c22 0.1 m f r37 10 d6 mmsd4148t1 r38 10 l3 6.8 m h d8b mbrb2535ctl 3672 v bst1 tp5 tp6 tp7 tp8 r32 11.8 k gnd r48 220 r49 3.3 k
cs51220 http://onsemi.com 16 package dimensions so16 d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs51220/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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